System-on-chip design flow for Software Defined Radio. (Flot de conception système sur puce pour radio logicielle)

Exploration architecturale pour la conception d'un système sur puce de vision robotique, adéquation algorithme-architecture d'un système embarqué temps-réel

Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone. Vers l'exploration à haut niveau de l'architecture

Résumé Les systèmes embarqués sur puce (ou system-on-chip, SoC) sont de plus en plus sophistiqués en intégrant de multiples fonctionnalités. Ils requièrent beaucoup de ressources pour améliorer les performances d’exécution. Leurs développements posent un véritable défi en raison, à la fois de leurs complexités et de leurs exigences en qualité de service. Cet article s’intéresse à la conception ...

Gaspard2 UML profile Documentation

This document describes the current UML profile of Gaspard2. This profile extends the UML semantics to allow the user to describe a SoC (System-on-Chip) in three steps: the application (behavior of the Soc), the hardware architecture, and the association of the application to the hardware architecture. The application is represented following a data flow model, but additional mechanisms permit ...

Lightweight verification of control flow policies on Java bytecode

This paper presents the enforcement of control flow policies for Java bytecode devoted to open and constrained devices. On-device enforcement of security policies mostly relies on run-time monitoring or inline checking code, which is not appropriate for strongly constrained devices such as mobile phones and smart-cards. We present a proof-carrying code approach with on-device lightweight verifi...

Formal Methods for Scheduling of Latency-Insensitive Designs

(Latency-Insensitive Design) theory was invented to deal with SoC timing closure issues, by allowing arbitrary fixed integer latencies on long global wires. Latencies are coped with using a resynchronization protocol that performs dynamic scheduling of data transportation. Functional behaviour is preserved. This dynamic scheduling is implemented using specific synchronous hardware elements: Rel...